The present invention relates to transferring to patterns a substrate, e.g., a semiconductor substrate.
For semiconductor devices or integrated circuit devices having a high degree of integration, extensive research has been made into developing schemes for improving device characteristics and securing an increased process margin. For example, semiconductor devices such as NAND type flash memory devices or DRAM memory devices have been developed to increase memory capacity and reduce the critical dimension (CD) of patterns making up such a device. For this reason, there are various limitations or problems associated with a micro lithography process, an etch process, and a chemical mechanical polishing (CMP) process required for the formation of patterns that make up a device on a wafer.
For example, pattern defects may occur in a light exposure process using micro lithography due to a reduction in pattern size. Examples of such pattern defects are; a pattern bridge, a phenomenon where patterns are undesirably connected; or a pattern necking, a phenomenon where the critical dimensions of a pattern is undesirably reduced, or the patterns are undesirably disconnected. In order to overcome such limitations associated with the processes, various methods have been proposed. For example, a method for changing or modifying a designed pattern layout, and a method for inserting dummy patterns into a designed layout, as assistant patterns.
The shape and function of such a dummy pattern depends on the characteristics of the layer which is required for fabrication of a semiconductor device and to which the dummy pattern is applied. Also, the method for creating such a dummy pattern and inserting the created dummy pattern depends on the designed circuitry layout. When the circuit pattern to be formed on a wafer is a gate pattern of a transistor, the dummy pattern may function as a gate assist pattern for assisting light exposure and etching of the gate pattern. The dummy pattern may be applied as a CMP assist dummy pattern to minimize the differences in polishing rates amongst different parts of a wafer due to the differences in topology of the wafer. In addition, a dummy pattern may be introduced which is capable of overcoming a pattern line width difference between a cell region and a peripheral region, thereby improving the process margin during light exposure and etch processes.
When the circuit pattern to be formed on a wafer is a gate pattern of a transistor, a line-shaped dummy pattern may be inserted as an assistant pattern for improving the process margin around a gate. Also, in the case of a memory device, a block-shaped dummy pattern may be inserted into a large empty area around a gate in a peripheral region. However, there is an increased possibility of a short circuit between the dummy pattern and the circuit pattern (e.g., around the bit line or metal interconnection layer) during the dummy pattern insertion process. As a result, it is difficult to perform the insertion of the dummy pattern in an automatic manner. For this reason, in conventional cases, the dummy pattern insertion is carried out manually.
For the creation of a dummy pattern, a rule dummy creation scheme may be taken into consideration. In this creation scheme the dummy pattern is created depending on rule data (including the dimensions and spacing of given patterns), the shape of the dummy pattern and the dimensions of the dummy pattern. A manual scheme based on the worker's determination may also be taken into consideration. In the rule dummy creation scheme, however, it is difficult to take into consideration parameters associated with the light exposure process. For this reason, there is a high possibility of a bridge between patterns or a collapse of patterns. Furthermore, in the process and design of the peripheral region, there may be unpredictable factors associated with creation and insertion of a dummy pattern unless light exposure conditions are taken into consideration. This is because 2-dimensional patterns are mainly arranged in the peripheral region.
On the other hand, in the manual scheme, it may take a relatively long time for the insertion of a dummy pattern. For example, in the case of a page buffer circuit arranged in a peripheral region of a multi-level cell (MLC) type flash memory device, the page buffer region may have a large width of about 700 μm. This large area would take a considerable amount of time to manually create and insert dummy patterns for the entire region. Furthermore, when dummy patterns are manually created in such a large region, the possibility of human error increases. As a result, it is difficult to obtain a circuit pattern without defects.
Therefore, development of a new dummy pattern insertion method is being required which can take into consideration light exposure process conditions, and thus, can secure stable light exposure process conditions, and can prevent a short circuit between a dummy pattern and a circuit pattern.